Framework for Mastering Digital Logic Fundamentals for Engineering Students Using Virtual Lab Simulation Tools

Abstract

Digital logic forms the foundational basis of computer science and electronics engineering education. However, students frequently encounter difficulties in transitioning from abstract Boolean representations to practical circuit implementation. This study proposes a structured pedagogical framework integrating virtual laboratory simulation tools to enhance conceptual understanding of digital logic fundamentals. A quasi-experimental pre-test/post-test design is employed to evaluate learning gains following a two-week structured intervention using digital circuit simulators. Quantitative analysis through paired sample t-tests and qualitative thematic analysis of student feedback are proposed to measure improvements in conceptual clarity, engagement, and confidence. The framework aims to bridge the theory–practice gap through interactive visualization, real-time feedback, and structured lab exercises. The study contributes an adaptable instructional model for improving foundational digital logic education in undergraduate engineering programs.